1. Technical Field
Various embodiments relate to a semiconductor circuit, and more particularly, to a semiconductor circuit and a leakage current test system using the same.
2. Related Art
In a semiconductor circuit, the number of pins is increasing as high speed processing of a large capacity is demanded.
Under this situation, a leakage current test circuit capable of self-testing pin leakage current, that is, performing a test inside a semiconductor circuit, is being used.
As an example of a conventional leakage current test circuit, there is disclosed “Contactless Digital Testing of IC Pin Leakage Currents (Stephen Sunter, Charles McDonald and Givargis Danialy)” in 2001 IEEE.
A leakage current test by a conventional leakage current test circuit is performed in such a manner that a pad is retained in a floating state for a predetermined time after being driven and then a voltage level variation by leakage current is measured.
However, the conventional leakage current test circuit has the following problems.
First, since it is impossible to solve a problem caused due to the fact that the capacitance of a pin to be applied to a pad is changed according to a process variation, the reliability of the test is likely to deteriorate.
Second, since a circuit configuration for generating a time from a state in which the pad is floated to until the voltage level variation is measured, that is, an internal delay time, is needed, a circuit area is likely to increase.